Simulation of I Bm Enterprise M. P. Mullen System/9000 Models 820

The discovery and removal of logic design errors early In the development cycle Is critical to timely availability of market-driven processor products. This paper describes the part played by sirnulation in the Verification of the high-end models of the iBM Enterprise System/9000" (ES/900OW) processor family, and how that effort advanced the state of the art of logic design simulation. The increased complexity of the ES/9000 design over that of the IBM Enterprise System/3090" (ES/3090") necessitated a larger sirnulation effort. New tools and methods were developed. Two simulation missions were established. Element sirnulation addressed ES/9000 functional elements (e.g., the storage controller) lndlvldually using the Compiled Enhanced Functional Simulator (CEFS), a software tool. System sirnulation tested two or more functional elements together using the Engineering Verification Engine (EVE), a special-purpose hardware parallel processor, and an attached IBM 3092 Processor Controller (PCE). The results achieved by simulation are discussed, together with the methods used and the Impact these results had on the overall verification of the ES/9000 Models 820 and 900. Introduction It has been documented [l-31 that the cost of uncovering hardware design errors is high when working with custom W I circuits. Engineering changes are costly in terms of time and engineering effort. Hardware design errors often prevent complete testing of a function, which may delay the discovery of additional errors. All of these factors bear directly on the profitability of a product. The potential revenue and market advantage lost because of a long engineering test-floor effort is very large in today's increasingly competitive mainframe marketplace. During the early planning stages of the IBM Enterprise System/9000m (ES/9000TM) processors, it was concluded that more errors had to be removed from the design before hardware was built. Simulation of logic design prior to its fabrication in hardware had played an important part in the verification of earlier machines. However, as then practiced, it would provide neither adequate nor expeditious verification of the ESl9000 machine architecture and its implementation. Its scope had to be increased. This paper discusses the part played by simulation in achieving this for the high-end processor models 820 and 900. Two simulation missions were established: element simulation and system simulation. Each major functional element of the central processor complex, or CPC (central processor, storage controller, I/O subsystem, and